Cisco Intel Xeon E7-4850 processor 2 GHz 24 MB L3

The Intel Xeon Processor E7-8800/4800/2800 Product Families is the second-generation chip multiprocessor (CMP) offering Intel QuickPath Interconnect (Intel QPI) technology in the Intel
Xeon MP processor family of processors. The Intel Xeon Processor E7-8800/4800/2800 Product Families implement up to ten multi-threaded (two thread) cores based upon the Intel Xeon Processor E7-8800/4800/2800 Product Families core design. A large, up to 30 MB, last-level cache (level 3), has been implemented to be shared across all active cores. The Intel Xeon Processor E7-8800/4800/2800 Product Families implement Intel QuickPath Interconnect technology to
replace the traditionally-implemented front-side bus. The Intel Xeon Processor E7-8800/4800/2800 Product Families provides four full width Intel QuickPath Interconnect links, sufficient to implement a glue-less (direct connect) four-processor socket and two IOH solutions, as well as scalable solutions based on OEM-developed external node controllers (referred to as XNC). The Intel Xeon Processor E7-8800/4800/2800 Product Families also integrate two memory controllers
supporting DDR3 memory technology to further enhance memory latency at higher memory capacity. The Intel Xeon Processor E7-8800/4800/2800 Product Families will be implemented on Intel 32-nm process technology and will be binary-compatible with applications running on previous
members of Intel's IA-32/IA-64 microprocessors.

New features of the Intel Xeon Processor E7-8800/4800/2800 Product Families include:
- Chip multiprocessor architecture with up to ten cores per socket
- Hyper-threaded cores, two threads
- Low-power, high-performance Intel Xeon Processor E7-8800/4800/2800 Product
- Families Core architecture
- Supports 48-bit virtual addressing and 44-bit physical addressing
- 32 KB Level 1 instruction cache with single bit error correction, and L1 Data cache:
- 32-KB Level 1 data cache with parity protection, or 16 KB Level 1 with ECC error
- correction and detection on data and on TAG
- 256 kB L2 instruction/data cache, ECC protected (SECDED)
- 30-MB LLC, instruction/data cache, ECC protected (Double Bit Error Correction,
- Triple bit Error Detection(DECTED), and SECDEC on TAG)
- Sideband read/write access to un-core logic via PECI and JTAG
- Support for sideband read access through PECI to core error log MSRs
- System management mode (SMM)
- Execute Disable Bit capability
- Direct-attach firmware to processor socket via serial flash interface — Supports commodity 1-, 4-, 8-MB SPI Flash ROM devices